Integrated circuit with multi-length power transistor segments

ABSTRACT

A monolithic power integrated circuit fabricated on a semiconductor die includes a control circuit and a first output high voltage field-effect transistor (HVFET) having source and drain segments substantially equal to a first length. A second output HVFET has source and drain segments substantially equal to a second length. At least one of the first and second output HVFETs is coupled to the control circuit. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductordevices; more specifically, to monolithic power integrated circuits andto methods of manufacturing power devices.

BACKGROUND OF THE INVENTION

Power integrated circuits (PICs) find application in an increasinglywide variety of electronic devices. Typically, PICs comprise one or morehigh-voltage field effect transistors (HVFETs) having a device structuresuch as those disclosed in U.S. Pat. No. 6,207,994 (“the '994 patent”),which is herein incorporated by reference. Each of the devices disclosedin the '994 patent has a source region and a drain region separated byan intermediate region. A gate structure is disposed over a thin oxidelayer over the metal-oxide-semiconductor (MOS) channel of the device. Inthe on state, a voltage is applied to the gate to cause a conductionchannel to form between the source and drain regions, thereby allowingcurrent to flow through the device. In the off state, the voltage on thegate is sufficiently low such that no conduction channel is formed inthe substrate, and thus no current flow occurs. In this condition, highvoltage is supported between the drain and source regions.

Most power integrated circuits (ICs) contain one or more output HVFETsthat control current flow through one or more external loads. By way ofexample, FIG. 7 of the '994 patent discloses an HVFET structure withinterdigitated source and drain regions that is commonly utilized as anoutput transistor in many types of power devices. In the design of aparticular PIC, these elongated source/drain segments may be replicatedto increase the current handling capability of the power device.

FIG. 1 shows a typical prior art PIC fabricated on a semiconductor die10 having an aspect ratio defined as the ratio of the length (L) to thewidth (W). Included on semiconductor die 10 is a control circuit 11 thatis utilized to control on/off switching of an output HVFET 12. In PICdesigns, it is customary to utilize a single standardized controlcircuit design coupled to a variety of HVFET layouts of differing sizes(e.g., number of segments) to create a family of devices with similarfunctionality, but with differing current handling capability. Forexample a family of PICs, each with differing current handlingcapabilities, may be created by increasing the number of parallelsegments of HVFET 12. According to this traditional approach, PICs withlarger current handling capability have a larger width (W) toaccommodate more source/drain segments, but the same length (L). Inother words, in prior art PIC designs, the length of the output HVFET 12is substantially constant, and equal to the length of control circuit11. PIC devices with more current handling capability have more segmentsadded in parallel, which increases the width of the semiconductor die.

To achieve maximum utilization of the package space that housessemiconductor die 10, control circuit 11 is usually designed with alength that is much larger than its width. In a typical PIC productfamily the smallest device is designed to be long and narrow (i.e.,large aspect ratio), with larger devices having an increased widthdimension due to the added number of HVFET segments (i.e., smalleraspect ratio). That is, the aspect ratio of larger devices decreases asmore segments are added.

Aspect ratio is a critical parameter in the design of a monolithic PIC.A PIC fabricated on a semiconductor die having a very large or verysmall aspect ratio often suffers from mechanical stress caused by themolding compound used to bond the die to the package. This stress canadversely change the electrical properties of the PIC circuitry. Asemiconductor die having a length that is substantially equal to itswidth (i.e., aspect ratio=1) minimizes stress and permits more efficientwire routing of the control circuit. The difficulty, however, is thatHVFET 12 is required to have elongated segments in order to achieve aspecific current handling capability. The package also has maximumcavity size. Thus, while it is desirable to manufacture a PIC on asemiconductor die having a substantially square shape, the need toprovide a product family with a range of current handling capabilitieswhich fits within a package cavity size has constrained the dimensionsof control circuit 11 and semiconductor die 10.

The solution of the prior art has been to provide a control circuit thathas a relatively narrow width and a much larger length that issubstantially equal to the maximum package cavity size. For example, inFIG. 1 the length of control circuit 11 is about four times its width.However, this causes inefficiencies in control circuit wiring. Anothersignificant shortcoming of this prior art approach is that PIC deviceswith small HVFETs (fewer segments) suffer from package stress problemscaused by high semiconductor die aspect ratio.

Thus, there is an unsatisfied need for an improved monolithic PIC designthat overcomes the problems of poor control circuit area efficiency andhigh PIC aspect ratio.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood more fully from the detaileddescription that follows and from the accompanying drawings, whichhowever, should not be taken to limit the invention to the specificembodiments shown, but are for explanation and understanding only.

FIG. 1 shows a circuit layout of a prior art monolithic power integratedcircuit.

FIG. 2 is circuit layout illustrating a monolithic power integratedcircuit according to one embodiment of the present invention.

FIG. 3 is a circuit schematic diagram that corresponds to the monolithicpower integrated circuit shown in FIG. 2.

DETAILED DESCRIPTION

An improved monolithic power integrated circuit is described. In thefollowing description, numerous specific details are set forth, such asdevice types, dimensions, circuit configurations, etc., in order toprovide a thorough understanding of the present invention. However,persons having ordinary skill in the semiconductor arts will appreciatethat these specific details may not be needed to practice the presentinvention.

FIG. 2 illustrates a circuit layout of a monolithic PIC according to oneembodiment of the present invention. The PIC of FIG. 2 is fabricated ona semiconductor die 20 and includes a first output HVFET 23 having a setof relatively short interdigitated source/drain segments, and a secondoutput HVFET 24 having a set of relatively long interdigitatedsource/drain segments. The segments of HVFETs 23 & 24 are placed on die20 in a manner that optimizes the layout of control circuit 21. Thearrangement of HVFETs 23 & 24 also improves the layout of the completePIC such that die 20 has a lower aspect ratio as compared to prior artdevices, even for implementations with low current handling capability.

As can be seen, output HVFET 23, with the short segments, is located ondie 20 adjacent the short, lateral side of control circuit 21. Controlcircuit 21 and HVFET 23 both have substantially the same width (W₁). Inthis embodiment, HVFET 23 has a length (L₁) that is less than the length(L₂) of control circuit 11. The total length (L) of semiconductor die 20is approximately equal to the sum of the lengths of HVFET 23 and controlcircuit 21 (L˜L₁+L₂).

In the embodiment of FIG. 2, output HVFET 24 is shown located on die 20adjacent the long, bottom side of control circuit 21, and also extendingbeneath the length of HVFET 23. The length of the segments of outputHVFET 24 is substantially equal to the length (L₂) of control circuit 21plus the length (L₁) of the segments of output HVFET 23. In other words,the short HVFET segments are placed alongside the short side of controlcircuit 11 such that the combined control circuit and short HVFETsegment length is substantially the same as the length of the long HVFETsegments of transistor 24.

The total width (W) of semiconductor die 20 is approximately equal tothe sum of the widths of control circuit 21 and HVFET 24 (W˜W₁+W₂). Tomanufacture a PIC device with increased current handling capability,more long segments are added in parallel to HVFET 24, which has theeffect of increasing the W₂ dimension and lowering the aspect ratio ofsemiconductor die 20.

Practitioners in the integrated circuit and semiconductor fabricationarts will appreciate that the embodiment shown in FIG. 2 permits controlcircuit 21 to have a layout with a smaller aspect ratio than prior artdesigns. In the implementation shown in FIG. 2, the length (L₂) ofcontrol circuit 21 is about three times its width (W₁). Furthermore, thenovel use and placement of multiple HVFETs having different segmentlengths results in an aspect ratio closer to 1.0 for the complete PIC.This means that a family of PIC devices, each with different currenthandling capability, may be manufactured on a semiconductor die 20, eachhaving an aspect ratio closer to 1.0. For the embodiment shown in FIG.2, the aspect ratio of die 20 is about 1.6.

With continuing reference to FIG. 2, a PIC device having a relativelysmall current handling capability may be realized by connecting controlcircuit 21 to HVFET 23, but not to HVFET 24. A PIC device havingincreased current handling capability may be implemented by connectingcontrol circuit 21 to both HVFET 23 and HVFET 24, or just to HVFET 24and not HVFET 23. PIC devices that provide even larger current handingcapability may be realized by increasing the number of long segment ofHVFET 24 during the layout and manufacturing of semiconductor die 20. Ineach case, the dimensions of control circuit 21 remain the same. Inaccordance with the present invention, a complete family of PIC deviceshaving a wide range of current handling capabilities may be implementedon a semiconductor die having an aspect ratio within a range of 0.5 to2.0.

It should be understood that even though the embodiment of FIG. 2illustrates two HVFETs with different length segments, there is norestriction on the number of HVFETs that may be included on die 20. Thatis, more than two HVFETs having different length segments may beincluded on die 20.

For example, a PIC with four output HVFETs may be implemented in whichtwo additional HVFETs are located side-by-side on die 20 above or belowHVFET 24. The two additional output HVFETs may have a combined segmentlength that is approximately equal to the sum of the lengths of HVFET 23and control circuit 21 (L˜L₁+L₂). In such as case, the segment lengthsof the two additional HVFETS may have an intermediate length that islonger than that of the short segments of HVFET 23, yet shorter than thelength of the long segments of HVFET 24. These additional HVFETs withintermediate length segments may be selectively coupled to controlcircuit 21 to implement a PIC device providing an intermediate range ofoutput current capacity.

FIG. 3 is a circuit schematic diagram that corresponds to the monolithicpower integrated circuit shown in FIG. 2. As explained previously,control circuit 21 may be selectively coupled to output HVFET 23 or tooutput HVFET 24, or to both HVFETs 23 & 24. This latter case is depictedby the dashed line showing a common connection to each of the threeterminals (i.e., source, drain, and gate) of the respective HVFETs.Alternatively, the HVFETs may have only one or two terminals coupledtogether (i.e., only the source terminals).

Persons of ordinary skill in the integrated circuit and semiconductorarts will appreciate that selective coupling between control circuit 21and one or both of the output HVFETs 23 & 24 may be achieved utilizing avariety of conventional techniques and circuits. For example, anoptional metal connection may be implemented during the layout andfabrication of the PIC. Alternatively, an ordinary on-chip switchingcircuit may be utilized for selectively coupling one or more of theoutput HVFETs to control circuit 21. This switching circuit may beincorporated into the layout of control circuit 21 and may comprise oneor more transistor switching devices (e.g., transmission gates).

Although the present invention has been described in conjunction withspecific embodiments, those of ordinary skill in the arts willappreciate that numerous modifications and alterations are well withinthe scope of the present invention. Accordingly, the specification anddrawings are to be regarded in an illustrative rather than a restrictivesense.

1. A monolithic power integrated circuit (PIC) fabricated on asemiconductor die comprising: a control circuit; a first output highvoltage field-effect transistor (HVFET) having source and drain segmentssubstantially equal to a first length; a second output HVFET havingsource and drain segments substantially equal to a second length;wherein at least one of the first and second output HVFETs is coupled tothe control circuit.
 2. The monolithic PIC of claim 1 wherein the firstlength is substantially longer than the second length.
 3. The monolithicPIC of claim 1 wherein the first and second HVFETS are coupled together.4. The monolithic PIC of claim 1 wherein the first output HVFET isdisposed on the semiconductor die adjacent a first side of the controlcircuit.
 5. The monolithic PIC of claim 4 wherein the second outputHVFET is disposed on the semiconductor die adjacent a second side of thecontrol circuit, wherein a combined length of the second output HVFETand the control circuit is substantially equal to the first length. 6.The monolithic PIC of claim 5 wherein the semiconductor die has asubstantially rectilinear shape with an aspect ratio within a range of0.5 to 2.0.
 7. A monolithic power integrated circuit (PIC) fabricated ona semiconductor die comprising: a control circuit; a plurality of outputhigh voltage field-effect transistors (HVFETs), each output HVFETincluding a plurality of segments of substantially equal length, one ormore of the output HVFETs being coupled to the control circuit; andwherein a segment length of at least one of the output HVFETs issubstantially longer than a segment length of any other of the outputHVFETs.
 8. The monolithic PIC of claim 7 wherein the plurality of outputHVFETS are coupled together to form a single output HVFET.
 9. Themonolithic PIC of claim 7 wherein the at least one of the output HVFETsis disposed on the semiconductor die adjacent a first side of thecontrol circuit.
 10. The monolithic PIC of claim 9 wherein a secondoutput HVFET is disposed on the semiconductor die adjacent a second sideof the control circuit, wherein a combined length of the second outputHVFET and the control circuit is substantially equal to the segmentlength of he at least one of the output HVFETs.
 11. The monolithic PICof claim 10 wherein the semiconductor die has a substantiallyrectilinear shape with an aspect ratio within a range of 0.5 to 2.0. 12.A power integrated circuit (PIC) fabricated on a semiconductor diecomprising: a control circuit occupying a first area of thesemiconductor die, the first area having a length and width; first andsecond output high voltage field-effect transistors (HVFETs) occupyingsecond and third areas of the semiconductor die, respectively, each ofthe second and third areas having a length and a width, the width of thesecond area being substantially equal to the width of the first area,wherein at least one of the first and second output HVFETs is coupled tothe control circuit.
 13. The PIC of claim 12 wherein the first andsecond output HVFETs each comprise interdigitated source and drainregions, and a gate, the interdigitated source and drain regions of thesecond output HVFET being substantially longer than the interdigitatedsource and drain regions of the first output HVFET.
 14. The PIC of claim13 wherein the semiconductor die has an aspect ratio within a range of0.5 to 2.0.
 15. The PIC of claim 12 wherein both the first and secondoutput HVFETs are coupled to the control circuit.
 16. A method ofmanufacturing a monolithic power integrated circuit (PIC) on asemiconductor die, the method comprising: locating a control circuit ina first area of the semiconductor die, the control circuit having alength that extends along a first side and a width that extends along asecond side; locating a first output high voltage field-effecttransistors (HVFET) adjacent the second side of the control circuit, thefirst output HVFET having a width substantially equal to the width ofthe control circuit; locating a second output HVFET adjacent the firstside of the control circuit, the second output HVFET having a lengthsubstantially equal to the length of the control circuit plus a lengthof the first output HVFET; and coupling the control circuit to at leastone of the first or second output HVFETs.
 17. The method of claim 16wherein the first and second output HVFETs each comprise interdigitatedsegments, the interdigitated segments of the second output HVFET beingsubstantially longer than the interdigitated segments of the firstoutput HVFET.
 18. The method of claim 16 wherein the semiconductor diehas an aspect ratio within a range of 0.5 to 2.0.
 19. A method ofmanufacturing a monolithic power integrated circuit (PIC) on asemiconductor die, the method comprising: locating a control circuit ina first area of the semiconductor die, the control circuit having alength that extends along a first side and a width that extends along asecond side; locating a first output high voltage field-effecttransistor (HVFET) adjacent the second side of the control circuit, thefirst output HVFET having a width substantially equal to the width ofthe control circuit; locating a second output HVFET adjacent the firstside of the control circuit, the second output HVFET having a lengthsubstantially equal to the length of the control circuit plus a lengthof the first output HVFET; and coupling the control circuit to the firstoutput HVFET such that the PIC has a first current handling capacity,or, alternatively, coupling the control circuit to the second outputHVFET such that the PIC has a second current handling capacity; whereinthe second current handling capacity is substantially greater than thefirst current handling capacity.
 20. The method of claim 19 wherein thefirst and second output HVFETs each comprise interdigitated segments,the interdigitated segments of the second output HVFET beingsubstantially longer than the interdigitated segments of the firstoutput HVFET.
 21. The method of claim 19 wherein the semiconductor diehas an aspect ratio within a range of 0.5 to 2.0.